This invention relates to microelectromechanical systems (MEMS) devices and methods of fabricating same, and more particularly to MEMS reflectors and beams and methods of fabricating same.
Optical communication systems are increasingly being used to communicate data, voice, multimedia and/or other communications. Optical communication systems may employ optical fibers and/or free space optical communication paths. It will be understood by those having skill in the art that optical communication systems may use optical radiation in the visible, ultraviolet, infrared and/or other portions of the electromagnetic radiation spectrum.
Reflectors, such as mirrors, are widely used in optical communications systems. For example, optical cross-connect (OXC) switches can include an array of reflectors to reflect optical energy from any switch input to any switch output. Similarly, add-drop optical switches also may use an array of reflectors such as mirrors to couple various optical paths.
It has been proposed to fabricate reflectors using microelectromechanical system (MEMS) technology. As is well known to those having skill in the art, MEMS devices are potentially low cost devices, due to the use of microelectronic fabrication techniques. New functionality also may be provided, because MEMS devices can be much smaller than conventional electromechanical devices.
One well-known and widely used process for fabricating MEMS devices is the MUMPs(trademark) process that is marketed by Cronos Integrated Microsystems, and is described in the MUMPS(trademark) Design Handbook, Revision 4.0, by the present inventor Koester et al., May 1999, the disclosure of which is hereby incorporated herein by reference in its entirety. In particular, as described in the MUMPs(trademark) Design Handbook, Section 1.2, the MUMPs process is a three-layer polysilicon surface micromachining process derived from work performed at the Berkeley Sensors and Actuators Center (BSAC) at the University of California in the late 1980s and early 1990s. Several modifications and enhancements have been made to increase the flexibility and versatility of the process for the multi-user environment.
The process begins with 100 mm n-type (100) silicon wafers of 1-2 xcexa9-cm resistivity. The surface of the wafers are first heavily doped with phosphorus in a standard diffusion furnace using POCl3 as the dopant source. This helps to reduce or prevent charge feedthrough to the substrate from electrostatic devices on the surface. Next, a 600 nm low-stress Low Pressure Chemical Vapor Deposition (LPCVD) silicon nitride layer is deposited on the wafers as an electrical isolation layer. This is followed directly by the deposition of a 500 nm LPCVD polysilicon film-Poly 0. Poly 0 is then patterned by photolithography, a process that includes the coating of the wafers with photoresist, exposure of the photoresist with the appropriate mask and developing the exposed photoresist to create the desired etch mask for subsequent pattern transfer into the underlying layer. After patterning the photoresist, the Poly 0 layer is then etched in a Reactive Ion Etch (RIE) system. A 2.0 xcexcm phosphosilicate glass (PSG) sacrificial layer is then deposited by LPCVD and annealed at 1050xc2x0 C. for one hour in argon. This layer of PSG, known as a first oxide, is removed at the end of the process to free the first mechanical layer of polysilicon. The sacrificial layer is lithographically patterned with a dimpled mask and the dimples are transferred into the sacrificial PSG layer by RIE. The nominal depth of the dimples is 750 nm. The wafers are then patterned with the third mask layer, ANCHOR1, and reactive ion etched. This step provides anchor holes that will be filed by the Poly 1 layer.
After etching ANCHOR1, the first structural layer of polysilicon (Poly 1) is deposited at a thickness of 2.0 xcexcm. A thin (200 nm) layer of PSG is deposited over the polysilicon and the wafer is annealed at 1050xc2x0 C. for one hour. The anneal dopes the polysilicon with phosphorus from the PSG layers both above and below it. The anneal also serves to significantly reduce the net stress in the Poly 1 layer. The polysilicon (and its PSG masking layer) is lithographically patterned using a mask designed to form the first structural layer POLY1. The PSG layer is etched to produce a hard mask for the subsequent polysilicon etch. The hard mask is more resistant to the polysilicon etch chemistry than the photoresist and ensures better transfer of the pattern into the polysilicon. After etching the polysilicon, the photoresist is stripped and the remaining oxide hard mask is removed by RIE.
After Poly 1 is etched, a second PSG layer (Second Oxide) is deposited and annealed. The Second Oxide is patterned using two different etch masks with different objectives. The POLY1xe2x80x94POLY2xe2x80x94VIA level provides for etch holes in the Second Oxide down to the Poly 1 layer. This provides a mechanical and electrical connection between the Poly 1 and Poly 2 layers. The POLY1xe2x80x94POLY2xe2x80x94VIA layer is lithographically patterned and etched by RIE. The ANCHOR2 level is provided to etch both the First and Second Oxide layers in one step, thereby eliminating any misalignment between separately etched holes. More importantly, the ANCHOR2 etch eliminates the need to make a cut in First Oxide unrelated to anchoring a Poly 1 structure, which needlessly exposes the substrate to subsequent processing that can damage either Poly 0 or Nitride. The ANCHOR2 layer is lithographically patterned and etched by RIE in the same way as POLY1xe2x80x94POLY2xe2x80x94VIA.
The second structural layer, Poly 2, is then deposited (1.5 xcexcm thick) followed by the deposition of 200 nm PSG. As with Poly 1, the thin PSG layer acts as both an etch mask and dopant source for Poly 2. The wafer is annealed for one hour at 1050xc2x0 C. to dope the polysilicon and reduce the residual film stress. The Poly 2 layer is lithographically patterned with the seventh mask (POLY2) and the PSG and polysilicon layers are etched by RIE using the same processing conditions as for Poly 1. The photoresist then is stripped and the masking oxide is removed. The final deposited layer in the MUMPs process is a 0.5 xcexcm metal layer including about 200 xc3x85 of a chromium adhesion layer and about 5000 xc3x85 of gold, that provides for probing, bonding, electrical routing and highly reflective mirror surfaces. The wafer is patterned lithographically with the eighth mask (METAL) and the metal is deposited and patterned using lift-off. The wafers are diced, sorted and shipped to the MUMPs user for sacrificial release and test. The release is performed by immersing the chip in a bath of 49% HF (room temperature) for 1.5-2 minutes. This is followed by several minutes in DI water and then alcohol to reduce stiction followed by at least 10 minutes in an oven at 1000xc2x0 C.
Microelectronic reflectors have been fabricated with the above-described MUMPs process, using a multilayer polysilicon base, a chromium adhesion layer and a gold reflective surface. Unfortunately, it may be difficult to form planar microelectronic reflectors using the above-described MUMPs process. In particular, stress gradients in the stacked polysilicon layers in conjunction with the internal stress of the deposited metal or metals, may produce reflectors that are not acceptably flat.
More particularly, it is known that phosphorus-doped polysilicon films may be slightly compressive. See, for example, the publication by Lee et al. entitled Effects of Phosphorus on Stress of Multi-Stacked Polysilicon Film and Single Crystalline Silicon, Journal of Micromechanical Micoengineering, Volume 9, pp. 252-263, Feb. 1999. Moreover, it is also known that the intrinsic film stress of most evaporated metal films is tensile. However, it may be difficult to fabricate a gold layer that has intrinsic film stress that is equal and opposite to the stress in the polysilicon layer or layers.
Finally, gold also has a high self-diffusion rate, and has been shown to undergo grain growth at temperatures as low as 90xc2x0 C. The tensile stress may increase in conjunction with this grain growth, as the volume of the gold film decreases. See for example, the publication by Koch entitled Microstructural Changes in Vapour-Deposited Silver, Copper and Gold Films Investigated by Internal Stress Measurements, Thin Solid Films, Vol. 140, 1986, pp. 217-226. Higher and higher temperatures show an increasing degree of stress. For at least these reasons, gold coated polysilicon reflectors, with or without an adhesion-promoting layer, may not be, or may not remain, planar.
It also is known to control stress in polysilicon layers fabricated by a MUMPs process by ion milling the second polysilicon layer. Unfortunately, it may be difficult to integrate ion milling with conventional microelectronic fabrication processes such as are used in MUMPs or other MEMS fabrication processing. Accordingly, in view of the above discussion, there continues to be a need for methods of fabricating flat microelectronic reflectors that can remain flat over time and/or temperature changes.
Embodiments of the present invention can provide methods of fabricating a microelectronic reflector by forming a first polysilicon layer on a microelectronic substrate, forming a first polysilicon doping layer, such as a first phosphosilicate glass (PSG) layer, on the first polysilicon layer, and reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer. A second polysilicon layer is formed on at least a portion of the first polysilicon layer from which the first PSG layer was removed. A second polysilicon doping layer, such as a second PSG layer, is formed on at least a second portion of the second polysilicon layer. Reactive ion etching is performed to remove the second PSG layer from at least a portion of the second polysilicon layer. A third polysilicon doping layer, such as a third PSG layer, then is formed on at least a portion of the second polysilicon layer from which the second PSG layer was removed. Reactive ion etching is performed to remove the third PSG layer from at least a portion of the second polysilicon layer. A reflective layer then is formed on at least a portion of the second polysilicon layer from which the third PSG layer was removed.
It has been found, according to the present invention, that by forming and reactive ion etching a third PSG layer, additional stress may be created in the first and/or second doped polysilicon layers that bends the ends of the doped first and/or second polysilicon layers towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to doped polysilicon layers on which the third PSG layer was not formed and reactive ion etched. This increased stress may be caused by the increased doping of the second and/or first polysilicon layer by the third PSG layer, by the surface modification that is created, by reactive ion etching to remove the third PSG layer and/or by other mechanisms. In any event, increased curvature in the combined first and second doped polysilicon layers thereby may be provided, without the need to perform ion milling. Stated differently, the radius of curvature may be modified.
According to other embodiments of the present invention, this increased stress may be counteracted by forming a stress-correcting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed, and then forming a reflective layer such as gold on at least a portion of the stress-correcting layer. The stress-correcting layer preferably comprises platinum, which can produce high stresses that can counteract the stresses in the first and second doped polysilicon layers, to thereby allow a flat mirror to be produced. The gold layer that is formed on the stress-correcting layer can act as a reflector. However, since the stress-correcting layer provides most, and preferably all, of the stress correction, flat reflectors may be provided that can remain flat over time and temperature. An adhesion-promoting layer such as titanium and/or chromium also may be provided between the stress-correcting layer and the second polysilicon layer.
According to other embodiments of the invention, a fourth PSG layer may be formed on the first polysilicon layer after reactive ion etching to remove the first PSG layer. Reactive ion etching may be performed to remove the fourth PSG layer from at least a portion of the first polysilicon layer. The second polysilicon layer then may be formed on at least a portion of the first polysilicon layer from which the fourth PSG layer has been removed.
Moreover, according to other embodiments of the invention, after forming each PSG layer, the PSG layer can be annealed, for example at about 1050xc2x0 C. for about one hour in argon, to dope the polysilicon with phosphorus from the PSG layer and/or to reduce the stress in the polysilicon layer. In other embodiments of the present invention, the titanium or chromium layer can be about 50 xc3x85 thick, the platinum layer can be at least about 200 xc3x85 thick, and preferably can be between about 200 xc3x85 and about 300 xc3x85 thick, and the gold layer can be about 50 xc3x85 thick. In yet other embodiments, the platinum layer can be at least twice as thick as the sum of the thickness of the titanium and/or chromium layer and the gold layer.
According to yet other embodiments of the present invention, the above-described metallization for microelectronic reflectors can be used with other doped polysilicon layer fabrication processes. Accordingly, a doped polysilicon base is formed on a microelectronic substrate. A metal stress-correcting layer is formed on at least a portion of the doped polysilicon base. A metal reflective layer is formed on at least a portion of the metal stress-correcting layer. Prior to forming the metal stress-correcting layer, a metal adhesion-promoting layer also may be formed on the doped polysilicon base. The composition and/or thicknesses of the metal adhesion-promoting layer, the metal stress-correcting layer and the metal reflective layer may be as was described above.
In other embodiments of the present invention, the doped polysilicon base may be fabricated by forming a doped polysilicon layer on a microelectronic substrate and treating the doped polysilicon layer to create stress therein that bends the ends of the polysilicon layer towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to an untreated doped polysilicon layer. A metal stress-correcting layer then may be formed that has stress therein that counters the stress in the treated doped polysilicon layer, to thereby create a planar reflector.
Microelectronic reflectors according to embodiments of the present invention can include a microelectronic substrate and a doped polysilicon base that is spaced apart from the microelectronic substrate. A metal stress-correcting layer is included on the doped polysilicon base, opposite the substrate. A metal reflective layer is included on the metal stress-correcting layer. A metal adhesion-promoting layer also may be provided between the doped polysilicon base and the metal stress-correcting layer. The compositions and/or dimensions of the metal adhesion-promoting layer, the metal stress-correcting layer and the metal reflective layer may be provided as was described above.
Yet other embodiments of the present invention can provide metallization for microelectronic reflectors that include a doped polysilicon base that is spaced apart from a microelectronic substrate. The metallization includes a platinum layer on the doped polysilicon base opposite the substrate, and a gold layer on the platinum layer. A titanium and/or chromium layer also may be provided between the doped polysilicon base and the platinum layer. The thicknesses thereof may be as was described above.
It also will be understood by those having skill in the art that embodiments of the above-described methods and structures may be used to form polysilicon MEMS beams that do not necessarily function as reflectors, but that are flat. Moreover, unlike conventional bimorph structures, these beams can remain flat over a wide range of temperatures and/or for an extended period of time. Accordingly, flat reflectors and/or beams may be provided by treating a polysilicon base to increase the bending of the ends thereof towards the substrate, and providing a metal stress-correcting layer to flatten the resultant structure.